205th Meeting of The Electrochemical Society
May 9-May 14, 2004
PROGRAM INFORMATION
G1 - Advanced Short-Time Thermal Processing for Si-Based CMOS Devices II
Electronics/Dielectric Science and Technology/High Temperature Materials/Aixtron GmbH/Akzo Nobel/Aldrich/Applied Materials/Axcelis Technologies/Genus/Mattson/Philips Lighting France/Vortek Industries/Intel
Monday, May 10, 2004
Conference Rooms 17 and 18, Level 3
Ultra-Shallow Junctions I
Co-Chairs: F. Roozeboom and W. Lerch
Ultra-Shallow Junctions II
Co-Chairs: P. Timans and Z.M. Zhang
Time | Abs# | Title |
14:00 | 241 |
Electronics Division Award Address: Defect Behavior and Control in Advanced CMOS Process Technologies - C. Claeys and E. Simoen (IMEC) |
14:30 | 242 |
Influence of Surface Chemistry on Ultrashallow Junction Formation - K. Dev and E.G. Seebauer (University of Illinois) |
14:50 | 243 |
Sub-30 nm Abrupt Junction Formation in Strained Si/Si1-XGeX CMOS Device - K. Lee, F. Cardone, P. Saunders, P. Kozlowski (IBM Thomas J Watson Research Center), P. Ronsheim, H. Zhu, J. Lee (IBM Microelectronics Division), J. Chu, K. Chan (IBM Thomas J Watson Research Center), and M. Leong (IBM Microelectronics Division) |
15:20 | 244 |
Stability of Ultrashallow Junction: Issue and Solution - L. Shao (University of Houston), P.E. Thompson (Naval Research Laboratory), J. Liu, and W.-K. Chu (University of Houston) |
15:40 | |
Twenty-Minute Intermission |
16:00 | 245 |
Solid Phase Epitaxy- Activation and Deactivation of Boron in Ultra-Shallow Junctions - W. Lerch, S. Paul, J. Nieb (Mattson Thermal Products GmBH), F. Cristiano, Y. Lamrani, P. Calvo, N. Cherakshin (CEMES/LAAS-CRNS), D.F. Downey, and E.A. Arevalo (Varian Semiconductor Equipment Associates) |
16:30 | 246 |
Ultra Shallow p^+/n Junctions Fabricated by Plasma Doping and All Solid State Laser Annealing - K. Tsutsui (Tokyo Institute of Technology), Y. Sasaki, C.-G. Jin, H. Tamura, B. Mizuno (Ultimate Junction Technologies Inc.), R. Higaki, T. Sato, K. Majima, S.-I. Ohmi, and H. Iwai (Tokyo Institute of Technology) |
16:50 | 247 |
Annihilation and Precipitation of Native Defects and Boron-Defect Complexes at the Si/SiO2 Interface - T. Kirichenko, D. Yu, G. Hwang, and S. Banerjee (University of Texas at Austin) |
17:10 | 248 |
Arsenic Deactivation and Transient Enhanced Diffusion in Crystalline Silicon: Role of Vacancies and Interstitials - S. Harrison, T. Edgar, and G. Hwang (University of Texas at Austin) |
Tuesday, May 11, 2004
Ultra-Shallow Junctions III
Co-Chairs: L. Chen and T.J. King
Time | Abs# | Title |
08:00 | 249 |
Gate-Source /Drain Extension Overlap Control with Angled Implants: TCAD Modeling Study - S. Thirupapuliyur, A. Al-Bayati, and A. Mayur (Applied Materials Inc.) |
08:20 | 250 |
Significant Improvement in Device Performance of Advanced Dynamic Random Access Memory by Hot Wall-Based Single Wafer Rapid Thermal Annealing - T. Setokubo, E. Nakano, K. Aizawa, H. Miyoshi, J. Yamamoto (Hiroshima Elpida Memory, Inc.), T. Fukada, and W.S. Yoo (WaferMasters, Inc.) |
08:40 | 251 |
Integration of Low and High Temperature Junction Anneals for 45nm CMOS - R. Lindsay, K. Henson, S. Severi, A. Satta, B. Pawlak (IMEC), A. Lauwers, R. Surdeanu (Philips Research Leuven), S. Mccoy, J. Gelpey (Vortek Industries Ltd), X. Pages (ASM Belgium), J. Kittl (Affiliated at Imec from TI), and K. Maex (IMEC) |
09:10 | |
Twenty-Minute Intermission |
New CMOS Technologies
Co-Chairs: M.C. Ozturk and W. Tsai
Time | Abs# | Title |
09:30 | 252 |
CMOS Optoelectronics - C.W. Liu and B.-C. Hsu (National Taiwan University) |
10:00 | 253 |
Device and Substrate Design for Sub-10NM Mosfets - M. Leong, B. Doris, J. Kedzierski, Z. Ren, K. Rim, M. Yang, H. Shang, and L. Chang (IBM) |
10:30 | 254 |
Low Thermal Budget Ge MOS Technology - C.O. Chui and K. Saraswat (Stanford University) |
11:00 | 255 |
Strained Ge MOSFETs: Devices and Process Technology - A. Ritenour, M. Lee (MIT), N. Lu, W. Bai (University of Texas- Austin), S. Yu, E. Fitzgerald (MIT), D.-L. Kwong (University of Texas- Austin), and D. Antoniadis (MIT) |
11:30 | 256 |
Transistor Scaling in the Nanoscale Era - S. Thompson (Intel Corporation) |
Silicide Contacts to Ultra-Shallow Junctions
Co-Chairs: L. Chen and M.C. Ozturk
Time | Abs# | Title |
14:00 | 257 |
Nickel SALICIDE Technology for Sub-100nm CMOS Devices - J.-P. Lu, D. Miles, A. Li-Fatou, Y.-Q. Xu, J. Zhao, A. Gurba, A. Griffin, Jr., B. Hornug, M. Hewson, T. Grider, D. Mercer, and C. Montgomery (Texas Instruments) |
14:30 | 258 |
The Effect of Ramp Rate - Short Process Time and Partial Reaction on Cobalt and Nickel Silicide Formation - X. Pages, K. Van Der Jeugd, V. Kuznetsov, E. Granneman (ASM International), A. Lauwers, and R. Lindsay (IMEC) |
14:50 | 259 |
Formation and Characterization of NiSi-Silicided n+p Shallow Junctions Using Implant Through Silicide and Low Temperature Furnace Annealing - C.-C. Wang and M.-C. Chen (National Chiao-Tung University) |
15:10 | 260 |
Nickel Silicide Optimized Process Formation for High Performance Sub-65nm CMOS Nodes. - B. Froment (STMicroelectronics) and V. Carron (CEA LETI) |
15:30 | |
Twenty-Minute Intermission |
Advanced Gate Stacks I: Oxynitrides and Polysilicon Gate Electrodes
Co-Chairs: G. Miner and G. Higashi
Time | Abs# | Title |
15:50 | 261 |
Reduced Poly-Si Gate Depletion Effect by Pulsed Excimer Laser Annealing - H.Y. Wong, H. Takeuchi, T.-J. King (Unversity of California, Berkeley), M. Ameen, and A. Agarwal (Axcelis Technologies) |
16:20 | 262 |
Ultra-Thin Silicon Oxynitride Gate-Dielectric Made by ECR Plasmas - G.A. Manera, J.A. Diniz, I. Doi, and J.W. Swart (UNICAMP) |
16:40 | 263 |
Characterization of Silicon Nitride Films for the Thin Film Transistor Gate Dielectric - S. Abbasi, H. Abu-Safe, H. Naseem, and W. Brown (University of Arkansas) |
17:00 | 264 |
LASER Anneal Technology for Enhancement of Poly-Silicon Dopant Activation - Y. Ma, K. Ahmed, K. Cunningham, C. Olsen, B. Leung, R. Mcintosh, A. Mayur, H. Liang, M. Yam, M. Castle, S. Muthukrishnan, P. Liu, M. Foad, G. Miner, and G. Higashi (Applied Materials) |
17:20 | 265 |
Further Optimization of Plasma Nitridation of Ultra-thin Oxides for 65 nm Node MOSFETs - P. Kraus, T.C. Chua (Applied Materials), A. Rothschild (IMEC), F. Cubaynes (Philips Research Leuven), A. Veloso, S. Mertens (IMEC), L. Date (Applied Materials Belgium), T. Bauer (Sandia National Laboratories), K. Ahmed, F. Nouri (Applied Materials), R. Schreutelkamp (Applied Materials Belgium), and M. Schaekers (IMEC) |
17:40 | 266 |
Enhancement of Manufacturability in Polycrystalline Silicon Process by Using Disilane Precursor At 65nm CMOS Technology - Y. Chen, H. Bu (Texas Instruments), S. Wang, K. Cunningham, and B. Spicer (Applied Materials) |
Wednesday, May 12, 2004
Advanced Gate Stacks II: High-K Gate Dielectrics
Co-Chairs: D.L. Kwong and T.J. King
Time | Abs# | Title |
10:00 | 267 |
Interface Composition and Band Alignment Issues in High-K Gate Stacks - E. Garfunkel, S. Sayan, L. Goncharova, T. Gustafsson, and D. Starodub (Rutgers University) |
10:30 | 268 |
A Novel Atomic Layer Deposition Process to Deposit Hafnium Silicate Thin Films - Y. Senzaki, M. Park, L. Bartholomew, and H. Chatham (Aviza Technology) |
10:50 | 269 |
Recent Progress In Gate Dielectric Scaling - G. Higashi (Applied Materials) |
11:20 | 270 |
HfTiO4 as a High-k Gate Insulator - F. Chen, M. Li (University of Minnesota), V. Afanas'ev (University of Leuven), W. Gladfelter, and S. Campbell (University of Minnesota) |
11:40 | 271 |
Electrical Charaterization in HfOxNy Gate Dielectric with Different Nitrogen Concentration Profiles Formed by Rapid Thermal Annealing - C.-L. Cheng and K.-S. Chang-Liao (National Tsing Hua University) |
Advanced Gate Stacks III: High-K Gate Dielectrics and Metal Gate Electrodes
Co-Chairs: E. Gusev and E. Garfunkel
Time | Abs# | Title |
14:00 | 272 |
Low Frequency Noise Characterization in HfAlO_x/SiO2 n-MOSFETs - T. Horikawa, N. Yasuda, W. Mizubayashi, K. Iwamoto, K. Tominaga, K. Akiyama, K. Yamamoto, H. Hisamatsu, H. Ota, T. Nabatame (MIRAI), and A. Toriumi (The University of Tokyo) |
14:30 | 273 |
Effects of Impurities In HfO2 - B. Xia, F. Chen (University of Minnesota), A. Stesmans (University of Leuven), W. Gladfelter, and S. Campbell (University of Minnesota) |
14:50 | 274 |
Factors Influencing the Threshold Voltages of Metal Oxide CMOS Devices - C. Hobbs, L. Fonseca, S. Samavedam, J. Grant, V. Dhandapani, B. Taylor, L. Dip, D. Triyoso, D. Gilmer, J. Schaeffer, R. Hegde, H. Tseng, B. White, and P. Tobin (Motorola) |
15:20 | |
Thirty-Minute Intermission |
Advanced Gate Stacks IV: High-K Dielectrics and Metal Gate Electrodes
Co-Chairs: E. Gusev and W. Maszara
Time | Abs# | Title |
15:50 | 275 |
Challenges in Integration of Metal Gate High K Dielectrics Gate Stacks - W. Tsai, L.A. Ragnarrson (Intel Corp), T. Schram, S. DeGendt, and M. Heyns (IMEC) |
16:20 | 276 |
Atomic Layer Deposition of Dielectrics and Electrodes for Embedded-DRAM Capacitor Cell in 90 nm Technology and Beyond - E. Gerritsen (Philips Semiconductors), N. Jourdan, M. Piazza (STMicroelectronics), D. Fraboulet (CEA-LETI), F. Monsieur (STMicroelectronics), J.F. Damlencourt, F. Martin (CEA-LETI), E. Mazaleyrat, K. Barla (STMicroelectronics), and G. Bartlett (Motorola) |
16:50 | 277 |
Fully Silicided Metal Gates for High Performance CMOS Technology - W. Maszara (AMD) |
17:20 | 278 |
Silicon and Precursors for Gate Dielectric and Electrode Applications - C.A. Hoover, S.H. Meiere, M.H. Litwin, J.P. Natwora, and J. Peck (Praxair, Inc.) |
17:40 | 279 |
TiCl_4 as a Precursor in the TiN Deposition by ALD or PEALD - K.-E. Elers, J. Winkler, and S. Marcus (ASM America Inc.) |
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