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Copper Electrodeposition for Via Filling
Osaka Prefecture University – Sakai, Japan
The researcher will be engaged in the development of new electrodeposition process for three dimensional packaging including TSV process; design copper deposition bath containing appropriate additives and fabricate copper filled deep vias on silicon wafer; use analytical techniques such as cyclic voltammetry, chronoamperometry, SEM, XRD, and so on. Presents of research at international conferences and publish in peer-reviewed journals are encouraged upon approval from collaborating companies and institutes.
